In some integrated circuit fabrication process, one or more hard masks may be used in processing operations to form various device features. Hard mask is usually used during patterning processes to pattern an underlying layer to form or define device features. In some process schemes, one or more patterned hard masks may also be temporarily employed to selectively expose one or more semiconductor regions for processing, while protecting the other semiconductor regions from being processed. Depending on the designed process, the hard masks may be removed after the processing operation is completed.
Ideally, the method to remove the hard mask results in complete removal of the hard mask layer(s) without leaving any residual hard mask material on the underlying layer and with minimum impact on the underlying layer. This can become challenging when the hard mask layer is conformally formed on a layer with non-planar or non-uniform surface topography. Moreover, conventional hard mask removal schemes for a semiconductor layer with topography are difficult to control and unreliable.
Accordingly, there remains a need for reliable hard mask removal methods that completely remove hard mask layers.